The device density of semiconductor integrated circuit chips ("IC" chips) has dramatically increased in the years since their initial introduction, such that millions of discrete components are now routinely included on a single IC chip. In addition, the clock speeds at which such chips operate has dramatically increased, such that digital signals at microwave frequencies are now being used in high performance systems. The increasing complexity of the devices being used, along with the higher speeds of such devices, have challenged the traditional methods of packaging chips.
Various multichip module structures have been developed to address the need to provide improved packaging for modern high-performance IC chips. One important reason for using multichip modules is to minimize signal propagation delay thereby improving system performance. Multichip module structures involve mounting a plurality of IC chips on one or more substrates to form a two- or three-dimensional array of chips. A substrate of a multichip module may include means for delivering power and ground to the individual chips mounted on the substrate, as well as signal paths for interconnecting the chips on the module, and for interconnecting these chips with other devices that are external to the module. Due to the complexity of providing all of the foregoing to each of the chips mounted on a substrate, such substrates are often fabricated as multilayer structures, with various patterned conductive layers being used for the required voltages and ground connections, and other conductive layers being used for signal lines. Interleaved between the patterned conductive layers are insulation layers to prevent shorting between the conductive layers.
Initially, the primary technology for forming multilayered multi-chip module substrates was ceramic-based, (sometimes referred to as "co-fired" ceramic). More recently, thin film structures, primarily based on the use of copper and polyimide, have become important due to the smaller line widths and layer thicknesses that can be realized, as well as the fact that polyimide has a more favorable dielectric constant than most ceramics. In addition, copper/polyimide structures are readily grown on silicon wafers, such that the much of the equipment and some of the techniques used in connection with the processing of semiconductor wafers can be employed in the fabrication of thin film multichip module substrates. Other multichip modules have been developed wherein the two technologies have been combined in multilayered structures comprising both ceramic portions and copper/polyimide portions.
Multilayered multichip module substrates, as just described, require means for connecting the various signal lines, power lines, ground lines and capacitors to a surface of the substrate so that they can be coupled to the IC chips mounted on the module. Such connections between the various layers and the surface of the module are commonly made using "vias" that run from the various layers to the surface or within the structure to interconnect layers.
A via typically comprises an aperture formed through one or more insulating layers as by removal of some of the material of the layer(s), which is then filled with a conductive material. Thus, a via has upper and lower ends at either side of the layer(s) through which it extends and is able to conduct electricity between these ends. The term via is sometimes used in the art to refer only to the aperture that is formed through one or more layers, with the understanding that the aperture is later to be filled with a conductive material. The particular usage of the word is generally obvious from the context, and both usages are employed in this specification. It is also common to speak of a "via opening" to describe the intermediate state of via fabrication after the aperture has been formed but before it is filled or lined with conductive material.
As discussed, one of the reasons for using multichip modules is due to the high number of interconnections that must be made with highly complex IC chips. When a large number of complex chips must be interconnected, the architecture of the multilayered chip module is commensurately complex. The need to provide separate vertical pathways through multiple layers of material presents designers with difficult topographical problems compounding the complexity of the structure. Area or "real estate" on the surface and within the layers of the module is at premium, such that it is desirable to form vias which occupy the minimum amount of area as possible. To do this it is desirable to form vias having a very high aspect ratio, i.e., the ratio of via depth to average via width or diameter.
Various methods are known in the prior art for forming via openings in multichip modules. In ceramic structures where the dimensions are relatively large, holes may simply be punched or otherwise mechanically formed in the various ceramic green sheet layers before they are hardened. Laser drilling of via openings is sometimes used for forming vias in both ceramic and thin film structures. Finally, wet and dry etching techniques may be used, and are particularly common for forming via openings in polyimide. It is noted that in many, if not most, uses of vias in multichip module substrates, the via openings are "blind," i.e., there is only an opening at one end. Vias are typically cylindrical in shape and have an aspect ratio which is defined by the diameter and the depth or height of the via. The present invention is particularly useful with vias wherein the diameter of the opening is less than 40 microns and the aspect ratio is 3:1 or greater.
Once via openings have been formed, they are then filled with a conductive material, typically a metal, which is compatible with the other materials used in the substrate. In the relatively very large via openings used ceramic substrate technology, the via openings in the ceramic green sheet layers are often simply mechanically filled with a conductive paste which hardens when the structure is fired. At the other size extreme, in actual IC chips, where via openings may be less than 0.5 microns in diameter, sputtering and chemical vapor deposition ("CVD") are typically used to fill via openings. However, plating, both electrolytic and electroless, is a preferred technology for filling via openings in thin film (e.g., copper/polyimide) substrates, due to its ability to rapidly deposit material and relative low cost of processing.
As the size has decreased due to the complexity of multichip module substrates and the "cost" of substrate real estate the ease of plating has commensurately decreased. In order to fill a via opening with a solid mass of conductive material by plating, it is necessary to first completely fill the opening with the plating solution. However, liquid surface tension and entrapped air within a via opening makes it difficult to ensure that the via opening to be plated becomes completely filled with plating solution. In addition, the surface characteristics of the via walls, such as its wetability, can impede filling the vias. If, for example, an air bubble is trapped in a via opening during plating, the result might be either the complete failure to grow the necessary mass of conductive material, or growth of a via with a void which has unacceptably poor conductivity.
There are several known prior art techniques to mitigate the foregoing problem, although all of them have limitations. One technique has been to add a surfactant to the plating solution to reduce its surface tension, thereby allowing it to more easier enter, "wet" and fill via openings. However, it is generally undesirable to add unnecessary and potentially contaminating chemicals to the plating mixture. Others techniques include vibrating the substrate to loosen any entrapped air bubbles and the use of a jet of liquid under pressure to force the plating liquid into the via openings. While these techniques have improved the ability to reliably plate small, blind vias, they are only partial solutions to the problem and there remains a need to improve the ability to plate within small, high aspect ratio via openings.
Accordingly, it is an object of the present invention to provide a reliable method of filling small, high aspect ratio via openings in a multichip module subject with a plating solution such that vias may be reliably formed within the substrate.
It is another object of the present invention to provide an apparatus in which the method of the present invention can be employed.
It is still a further object of the present invention to provide a reliable, relatively low-cost, effective method and apparatus for filling via openings with a plating solution or other liquid used in connection with a plating process.